/**
 ****************************************************************************************************
 * @file        sys.c
 * @author      ԭŶ(ALIENTEK)
 * @version     V1.0
 * @date        2020-04-17
 * @brief       ϵͳʼ(ʱ/жϹ/GPIOõ)
 * @license     Copyright (c) 2020-2032, ӿƼ޹˾
 ****************************************************************************************************
 * @attention
 *
 * ʵƽ̨:ԭ MiniSTM32 V4
 * Ƶ:www.yuanzige.com
 * ̳:www.openedv.com
 * ˾ַ:www.alientek.com
 * ַ:openedv.taobao.com
 *
 * ޸˵
 * V1.0 20211103
 * һη
 *
 ****************************************************************************************************
 */

#include "sys.h"


/**
 * @brief       жƫƵַ
 * @param       baseaddr: ַ
 * @param       offset: ƫ(0, 0X100ı)
 * @retval      
 */
void sys_nvic_set_vector_table(uint32_t baseaddr, uint32_t offset)
{
    /* NVICƫƼĴ,VTOR9λ,[8:0] */
    SCB->VTOR = baseaddr | (offset & (uint32_t)0xFFFFFE00);
}

/**
 * @brief       ִ: WFIָ(ִָ͹״̬, ȴжϻ)
 * @param       
 * @retval      
 */
void sys_wfi_set(void)
{
    __ASM volatile("wfi");
}

/**
 * @brief       رж(ǲfaultNMIж)
 * @param       
 * @retval      
 */
void sys_intx_disable(void)
{
    __ASM volatile("cpsid i");
}

/**
 * @brief       ж
 * @param       
 * @retval      
 */
void sys_intx_enable(void)
{
    __ASM volatile("cpsie i");
}

/**
 * @brief       ջַ
 * @note        ĺX, MDK, ʵû
 * @param       addr: ջַ
 * @retval      
 */
void sys_msr_msp(uint32_t addr)
{
    __set_MSP(addr);  /* ջַ */
}

/**
 * @brief       ģʽ
 * @param       
 * @retval      
 */
void sys_standby(void)
{
    __HAL_RCC_PWR_CLK_ENABLE();    /* ʹܵԴʱ */
    SET_BIT(PWR->CR, PWR_CR_PDDS); /* ģʽ */
}

/**
 * @brief       ϵͳλ
 * @param       
 * @retval      
 */
void sys_soft_reset(void)
{
    NVIC_SystemReset();
}

/**
 * @brief       ϵͳʱӳʼ
 * @param       plln: PLLƵϵ(PLLƵ), ȡֵΧ: 2~16
                жλʱѾSystemInit()гʼ
 * @retval      
 */
void sys_stm32_clock_init(uint32_t plln)
{
    HAL_StatusTypeDef ret = HAL_ERROR;
    RCC_OscInitTypeDef rcc_osc_init = {0};
    RCC_ClkInitTypeDef rcc_clk_init = {0};

    rcc_osc_init.OscillatorType = RCC_OSCILLATORTYPE_HSE;       /* ѡҪHSE */
    rcc_osc_init.HSEState = RCC_HSE_ON;                         /* HSE */
    rcc_osc_init.HSEPredivValue = RCC_HSE_PREDIV_DIV1;          /* HSEԤƵϵ */
    rcc_osc_init.PLL.PLLState = RCC_PLL_ON;                     /* PLL */
    rcc_osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE;             /* PLLʱԴѡHSE */
    rcc_osc_init.PLL.PLLMUL = plln;                             /* PLLƵϵ */
    ret = HAL_RCC_OscConfig(&rcc_osc_init);                     /* ʼ */

    if (ret != HAL_OK)
    {
        while (1);                                              /* ʱӳʼʧܣ֮ĳ򽫿޷ִУԼĴ */
    }

    /* ѡPLLΪϵͳʱԴHCLK,PCLK1PCLK2*/
    rcc_clk_init.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
    rcc_clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;        /* ϵͳʱPLL */
    rcc_clk_init.AHBCLKDivider = RCC_SYSCLK_DIV1;               /* AHBƵϵΪ1 */
    rcc_clk_init.APB1CLKDivider = RCC_HCLK_DIV2;                /* APB1ƵϵΪ2 */
    rcc_clk_init.APB2CLKDivider = RCC_HCLK_DIV1;                /* APB2ƵϵΪ1 */
    ret = HAL_RCC_ClockConfig(&rcc_clk_init, FLASH_LATENCY_2);  /* ͬʱFLASHʱΪ2WSҲ3CPUڡ */

    if (ret != HAL_OK)
    {
        while (1);                                              /* ʱӳʼʧܣ֮ĳ򽫿޷ִУԼĴ */
    }
}


