int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,

                              int access_type, int mmu_idx, int is_softmmu)

{

    uint32_t phys_addr;

    target_ulong page_size;

    int prot;

    int ret, is_user;



    is_user = mmu_idx == MMU_USER_IDX;

    ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,

                        &page_size);

    if (ret == 0) {

        /* Map a single [sub]page.  */

        phys_addr &= ~(uint32_t)0x3ff;

        address &= ~(uint32_t)0x3ff;

        tlb_set_page (env, address, phys_addr, prot | PAGE_EXEC, mmu_idx,

                      page_size);

        return 0;

    }



    if (access_type == 2) {

        env->cp15.c5_insn = ret;

        env->cp15.c6_insn = address;

        env->exception_index = EXCP_PREFETCH_ABORT;

    } else {

        env->cp15.c5_data = ret;

        if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))

            env->cp15.c5_data |= (1 << 11);

        env->cp15.c6_data = address;

        env->exception_index = EXCP_DATA_ABORT;

    }

    return 1;

}

int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,

                              int access_type, int mmu_idx, int is_softmmu)

{

    uint32_t phys_addr;

    target_ulong page_size;

    int prot;

    int ret, is_user;



    is_user = mmu_idx == MMU_USER_IDX;

    ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,

                        &page_size);

    if (ret == 0) {

        

        phys_addr &= ~(uint32_t)0x3ff;

        address &= ~(uint32_t)0x3ff;

        tlb_set_page (env, address, phys_addr, prot | PAGE_EXEC, mmu_idx,

                      page_size);

        return 0;

    }



    if (access_type == 2) {

        env->cp15.c5_insn = ret;

        env->cp15.c6_insn = address;

        env->exception_index = EXCP_PREFETCH_ABORT;

    } else {

        env->cp15.c5_data = ret;

        if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))

            env->cp15.c5_data |= (1 << 11);

        env->cp15.c6_data = address;

        env->exception_index = EXCP_DATA_ABORT;

    }

    return 1;

}

int FUNC_0 (CPUState *VAR_0, target_ulong VAR_1,

                              int VAR_2, int VAR_3, int VAR_4)

{

    uint32_t phys_addr;

    target_ulong page_size;

    int VAR_5;

    int VAR_6, VAR_7;



    VAR_7 = VAR_3 == MMU_USER_IDX;

    VAR_6 = get_phys_addr(VAR_0, VAR_1, VAR_2, VAR_7, &phys_addr, &VAR_5,

                        &page_size);

    if (VAR_6 == 0) {

        

        phys_addr &= ~(uint32_t)0x3ff;

        VAR_1 &= ~(uint32_t)0x3ff;

        tlb_set_page (VAR_0, VAR_1, phys_addr, VAR_5 | PAGE_EXEC, VAR_3,

                      page_size);

        return 0;

    }



    if (VAR_2 == 2) {

        VAR_0->cp15.c5_insn = VAR_6;

        VAR_0->cp15.c6_insn = VAR_1;

        VAR_0->exception_index = EXCP_PREFETCH_ABORT;

    } else {

        VAR_0->cp15.c5_data = VAR_6;

        if (VAR_2 == 1 && arm_feature(VAR_0, ARM_FEATURE_V6))

            VAR_0->cp15.c5_data |= (1 << 11);

        VAR_0->cp15.c6_data = VAR_1;

        VAR_0->exception_index = EXCP_DATA_ABORT;

    }

    return 1;

}

int FUNC_0 (CPUState *VAR_0, target_ulong VAR_1,
int VAR_2, int VAR_3, int VAR_4)
{ uint32_t phys_addr; target_ulong page_size; int VAR_5; int VAR_6, VAR_7; VAR_7 = VAR_3 == MMU_USER_IDX; VAR_6 = get_phys_addr(VAR_0, VAR_1, VAR_2, VAR_7, &phys_addr, &VAR_5,
&page_size); if (VAR_6 == 0) { phys_addr &= ~(uint32_t)0x3ff; VAR_1 &= ~(uint32_t)0x3ff; tlb_set_page (VAR_0, VAR_1, phys_addr, VAR_5 | PAGE_EXEC, VAR_3,
page_size); return 0; } if (VAR_2 == 2) { VAR_0->cp15.c5_insn = VAR_6; VAR_0->cp15.c6_insn = VAR_1; VAR_0->exception_index = EXCP_PREFETCH_ABORT; } else { VAR_0->cp15.c5_data = VAR_6; if (VAR_2 == 1 && arm_feature(VAR_0, ARM_FEATURE_V6))
VAR_0->cp15.c5_data |= (1 << 11); VAR_0->cp15.c6_data = VAR_1; VAR_0->exception_index = EXCP_DATA_ABORT; } return 1; }