static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)

{

    if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {

        if (sregnames[sr].name) {

            qemu_log("SR %s is not configured\n", sregnames[sr].name);

        } else {

            qemu_log("SR %d is not implemented\n", sr);

        }

        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);

    } else if (!(sregnames[sr].access & access)) {

        static const char * const access_text[] = {

            [SR_R] = "rsr",

            [SR_W] = "wsr",

            [SR_X] = "xsr",

        };

        assert(access < ARRAY_SIZE(access_text) && access_text[access]);

        qemu_log("SR %s is not available for %s\n", sregnames[sr].name,

                access_text[access]);

        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);

    }

}

static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)

{

    if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {

        if (sregnames[sr].name) {

            qemu_log("SR %s is not configured\n", sregnames[sr].name);

        } else {

            qemu_log("SR %d is not implemented\n", sr);

        }

        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);

    } else if (!(sregnames[sr].access & access)) {

        static const char * const access_text[] = {

            [SR_R] = "rsr",

            [SR_W] = "wsr",

            [SR_X] = "xsr",

        };

        assert(access < ARRAY_SIZE(access_text) && access_text[access]);

        qemu_log("SR %s is not available for %s\n", sregnames[sr].name,

                access_text[access]);

        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);

    }

}

static void gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
static void FUNC_0(DisasContext *VAR_0, uint32_t VAR_1, unsigned VAR_2)

{

    if (!xtensa_option_bits_enabled(VAR_0->config, sregnames[VAR_1].opt_bits)) {

        if (sregnames[VAR_1].name) {

            qemu_log("SR %s is not configured\n", sregnames[VAR_1].name);

        } else {

            qemu_log("SR %d is not implemented\n", VAR_1);

        }

        gen_exception_cause(VAR_0, ILLEGAL_INSTRUCTION_CAUSE);

    } else if (!(sregnames[VAR_1].VAR_2 & VAR_2)) {

        static const char * const VAR_3[] = {

            [SR_R] = "rsr",

            [SR_W] = "wsr",

            [SR_X] = "xsr",

        };

        assert(VAR_2 < ARRAY_SIZE(VAR_3) && VAR_3[VAR_2]);

        qemu_log("SR %s is not available for %s\n", sregnames[VAR_1].name,

                VAR_3[VAR_2]);

        gen_exception_cause(VAR_0, ILLEGAL_INSTRUCTION_CAUSE);

    }

}

static void FUNC_0(DisasContext *VAR_0, uint32_t VAR_1, unsigned VAR_2)
{ if (!xtensa_option_bits_enabled(VAR_0->config, sregnames[VAR_1].opt_bits)) { if (sregnames[VAR_1].name) { qemu_log("SR %s is not configured\n", sregnames[VAR_1].name); } else { qemu_log("SR %d is not implemented\n", VAR_1); } gen_exception_cause(VAR_0, ILLEGAL_INSTRUCTION_CAUSE); } else if (!(sregnames[VAR_1].VAR_2 & VAR_2)) { static const char * const VAR_3[] = { [SR_R] = "rsr",
[SR_W] = "wsr",
[SR_X] = "xsr",
}; assert(VAR_2 < ARRAY_SIZE(VAR_3) && VAR_3[VAR_2]); qemu_log("SR %s is not available for %s\n", sregnames[VAR_1].name,
VAR_3[VAR_2]); gen_exception_cause(VAR_0, ILLEGAL_INSTRUCTION_CAUSE); } }