void cpu_dump_state (CPUState *env, FILE *f, 

                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),

                     int flags)

{

    uint32_t c0_status;

    int i;

    

    cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",

                env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);

    for (i = 0; i < 32; i++) {

        if ((i & 3) == 0)

            cpu_fprintf(f, "GPR%02d:", i);

        cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i]);

        if ((i & 3) == 3)

            cpu_fprintf(f, "\n");

    }



    c0_status = env->CP0_Status;



    cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",

                c0_status, env->CP0_Cause, env->CP0_EPC);

    cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",

                env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);

    if (c0_status & (1 << CP0St_CU1))

        fpu_dump_state(env, f, cpu_fprintf, flags);

#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)

    cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);

#endif

}

void cpu_dump_state (CPUState *env, FILE *f, 

                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),

                     int flags)

{

    uint32_t c0_status;

    int i;

    

    cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",

                env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);

    for (i = 0; i < 32; i++) {

        if ((i & 3) == 0)

            cpu_fprintf(f, "GPR%02d:", i);

        cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i]);

        if ((i & 3) == 3)

            cpu_fprintf(f, "\n");

    }



    c0_status = env->CP0_Status;



    cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",

                c0_status, env->CP0_Cause, env->CP0_EPC);

    cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",

                env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);

    if (c0_status & (1 << CP0St_CU1))

        fpu_dump_state(env, f, cpu_fprintf, flags);

#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)

    cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);

#endif

}

void FUNC_0 (CPUState *VAR_0, FILE *VAR_3, 

                     int (*VAR_2)(FILE *VAR_3, const char *VAR_3, ...),

                     int VAR_4)

{

    uint32_t c0_status;

    int VAR_5;

    

    VAR_2(VAR_3, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",

                VAR_0->PC, VAR_0->HI, VAR_0->LO, VAR_0->hflags, VAR_0->btarget, VAR_0->bcond);

    for (VAR_5 = 0; VAR_5 < 32; VAR_5++) {

        if ((VAR_5 & 3) == 0)

            VAR_2(VAR_3, "GPR%02d:", VAR_5);

        VAR_2(VAR_3, " %s " TARGET_FMT_lx, regnames[VAR_5], VAR_0->gpr[VAR_5]);

        if ((VAR_5 & 3) == 3)

            VAR_2(VAR_3, "\n");

    }



    c0_status = VAR_0->CP0_Status;



    VAR_2(VAR_3, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",

                c0_status, VAR_0->CP0_Cause, VAR_0->CP0_EPC);

    VAR_2(VAR_3, "    Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",

                VAR_0->CP0_Config0, VAR_0->CP0_Config1, VAR_0->CP0_LLAddr);

    if (c0_status & (1 << CP0St_CU1))

        fpu_dump_state(VAR_0, VAR_3, VAR_2, VAR_4);

#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)

    cpu_mips_check_sign_extensions(VAR_0, VAR_3, VAR_2, VAR_4);

#endif

}

void FUNC_0 (CPUState *VAR_0, FILE *VAR_3,
int (*VAR_2)(FILE *VAR_3, const char *VAR_3, ...),
int VAR_4)
{ uint32_t c0_status; int VAR_5; VAR_2(VAR_3, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
VAR_0->PC, VAR_0->HI, VAR_0->LO, VAR_0->hflags, VAR_0->btarget, VAR_0->bcond); for (VAR_5 = 0; VAR_5 < 32; VAR_5++) { if ((VAR_5 & 3) == 0)
VAR_2(VAR_3, "GPR%02d:", VAR_5); VAR_2(VAR_3, " %s " TARGET_FMT_lx, regnames[VAR_5], VAR_0->gpr[VAR_5]); if ((VAR_5 & 3) == 3)
VAR_2(VAR_3, "\n"); } c0_status = VAR_0->CP0_Status; VAR_2(VAR_3, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TARGET_FMT_lx "\n",
c0_status, VAR_0->CP0_Cause, VAR_0->CP0_EPC); VAR_2(VAR_3, "    Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
VAR_0->CP0_Config0, VAR_0->CP0_Config1, VAR_0->CP0_LLAddr); if (c0_status & (1 << CP0St_CU1))
fpu_dump_state(VAR_0, VAR_3, VAR_2, VAR_4); #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
cpu_mips_check_sign_extensions(VAR_0, VAR_3, VAR_2, VAR_4); #endif
}