void tlb_set_page(CPUArchState *env, target_ulong vaddr,

                  target_phys_addr_t paddr, int prot,

                  int mmu_idx, target_ulong size)

{

    MemoryRegionSection *section;

    unsigned int index;

    target_ulong address;

    target_ulong code_address;

    uintptr_t addend;

    CPUTLBEntry *te;

    target_phys_addr_t iotlb;



    assert(size >= TARGET_PAGE_SIZE);

    if (size != TARGET_PAGE_SIZE) {

        tlb_add_large_page(env, vaddr, size);

    }

    section = phys_page_find(paddr >> TARGET_PAGE_BITS);

#if defined(DEBUG_TLB)

    printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx

           " prot=%x idx=%d pd=0x%08lx\n",

           vaddr, paddr, prot, mmu_idx, pd);

#endif



    address = vaddr;

    if (!(memory_region_is_ram(section->mr) ||

          memory_region_is_romd(section->mr))) {

        /* IO memory case (romd handled later) */

        address |= TLB_MMIO;

    }

    if (memory_region_is_ram(section->mr) ||

        memory_region_is_romd(section->mr)) {

        addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)

        + memory_region_section_addr(section, paddr);

    } else {

        addend = 0;

    }



    code_address = address;

    iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, prot,

                                            &address);



    index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    env->iotlb[mmu_idx][index] = iotlb - vaddr;

    te = &env->tlb_table[mmu_idx][index];

    te->addend = addend - vaddr;

    if (prot & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (prot & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (prot & PAGE_WRITE) {

        if ((memory_region_is_ram(section->mr) && section->readonly)

            || memory_region_is_romd(section->mr)) {

            /* Write access calls the I/O callback.  */

            te->addr_write = address | TLB_MMIO;

        } else if (memory_region_is_ram(section->mr)

                   && !cpu_physical_memory_is_dirty(

                           section->mr->ram_addr

                           + memory_region_section_addr(section, paddr))) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

void tlb_set_page(CPUArchState *env, target_ulong vaddr,

                  target_phys_addr_t paddr, int prot,

                  int mmu_idx, target_ulong size)

{

    MemoryRegionSection *section;

    unsigned int index;

    target_ulong address;

    target_ulong code_address;

    uintptr_t addend;

    CPUTLBEntry *te;

    target_phys_addr_t iotlb;



    assert(size >= TARGET_PAGE_SIZE);

    if (size != TARGET_PAGE_SIZE) {

        tlb_add_large_page(env, vaddr, size);

    }

    section = phys_page_find(paddr >> TARGET_PAGE_BITS);

#if defined(DEBUG_TLB)

    printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx

           " prot=%x idx=%d pd=0x%08lx\n",

           vaddr, paddr, prot, mmu_idx, pd);

#endif



    address = vaddr;

    if (!(memory_region_is_ram(section->mr) ||

          memory_region_is_romd(section->mr))) {

        

        address |= TLB_MMIO;

    }

    if (memory_region_is_ram(section->mr) ||

        memory_region_is_romd(section->mr)) {

        addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)

        + memory_region_section_addr(section, paddr);

    } else {

        addend = 0;

    }



    code_address = address;

    iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, prot,

                                            &address);



    index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    env->iotlb[mmu_idx][index] = iotlb - vaddr;

    te = &env->tlb_table[mmu_idx][index];

    te->addend = addend - vaddr;

    if (prot & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (prot & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (prot & PAGE_WRITE) {

        if ((memory_region_is_ram(section->mr) && section->readonly)

            || memory_region_is_romd(section->mr)) {

            

            te->addr_write = address | TLB_MMIO;

        } else if (memory_region_is_ram(section->mr)

                   && !cpu_physical_memory_is_dirty(

                           section->mr->ram_addr

                           + memory_region_section_addr(section, paddr))) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

void FUNC_0(CPUArchState *VAR_0, target_ulong VAR_1,

                  target_phys_addr_t VAR_2, int VAR_3,

                  int VAR_4, target_ulong VAR_5)

{

    MemoryRegionSection *section;

    unsigned int VAR_6;

    target_ulong address;

    target_ulong code_address;

    uintptr_t addend;

    CPUTLBEntry *te;

    target_phys_addr_t iotlb;



    assert(VAR_5 >= TARGET_PAGE_SIZE);

    if (VAR_5 != TARGET_PAGE_SIZE) {

        tlb_add_large_page(VAR_0, VAR_1, VAR_5);

    }

    section = phys_page_find(VAR_2 >> TARGET_PAGE_BITS);

#if defined(DEBUG_TLB)

    printf("FUNC_0: VAR_1=" TARGET_FMT_lx " VAR_2=0x" TARGET_FMT_plx

           " VAR_3=%x idx=%d pd=0x%08lx\n",

           VAR_1, VAR_2, VAR_3, VAR_4, pd);

#endif



    address = VAR_1;

    if (!(memory_region_is_ram(section->mr) ||

          memory_region_is_romd(section->mr))) {

        

        address |= TLB_MMIO;

    }

    if (memory_region_is_ram(section->mr) ||

        memory_region_is_romd(section->mr)) {

        addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)

        + memory_region_section_addr(section, VAR_2);

    } else {

        addend = 0;

    }



    code_address = address;

    iotlb = memory_region_section_get_iotlb(VAR_0, section, VAR_1, VAR_2, VAR_3,

                                            &address);



    VAR_6 = (VAR_1 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    VAR_0->iotlb[VAR_4][VAR_6] = iotlb - VAR_1;

    te = &VAR_0->tlb_table[VAR_4][VAR_6];

    te->addend = addend - VAR_1;

    if (VAR_3 & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (VAR_3 & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (VAR_3 & PAGE_WRITE) {

        if ((memory_region_is_ram(section->mr) && section->readonly)

            || memory_region_is_romd(section->mr)) {

            

            te->addr_write = address | TLB_MMIO;

        } else if (memory_region_is_ram(section->mr)

                   && !cpu_physical_memory_is_dirty(

                           section->mr->ram_addr

                           + memory_region_section_addr(section, VAR_2))) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

void FUNC_0(CPUArchState *VAR_0, target_ulong VAR_1,
target_phys_addr_t VAR_2, int VAR_3,
int VAR_4, target_ulong VAR_5)
{ MemoryRegionSection *section; unsigned int VAR_6; target_ulong address; target_ulong code_address; uintptr_t addend; CPUTLBEntry *te; target_phys_addr_t iotlb; assert(VAR_5 >= TARGET_PAGE_SIZE); if (VAR_5 != TARGET_PAGE_SIZE) { tlb_add_large_page(VAR_0, VAR_1, VAR_5); } section = phys_page_find(VAR_2 >> TARGET_PAGE_BITS); #if defined(DEBUG_TLB)
printf("FUNC_0: VAR_1=" TARGET_FMT_lx " VAR_2=0x" TARGET_FMT_plx
" VAR_3=%x idx=%d pd=0x%08lx\n",
VAR_1, VAR_2, VAR_3, VAR_4, pd); #endif
address = VAR_1; if (!(memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr))) { address |= TLB_MMIO; } if (memory_region_is_ram(section->mr) ||
memory_region_is_romd(section->mr)) { addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)
+ memory_region_section_addr(section, VAR_2); } else { addend = 0; } code_address = address; iotlb = memory_region_section_get_iotlb(VAR_0, section, VAR_1, VAR_2, VAR_3,
&address); VAR_6 = (VAR_1 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); VAR_0->iotlb[VAR_4][VAR_6] = iotlb - VAR_1; te = &VAR_0->tlb_table[VAR_4][VAR_6]; te->addend = addend - VAR_1; if (VAR_3 & PAGE_READ) { te->addr_read = address; } else { te->addr_read = -1; } if (VAR_3 & PAGE_EXEC) { te->addr_code = code_address; } else { te->addr_code = -1; } if (VAR_3 & PAGE_WRITE) { if ((memory_region_is_ram(section->mr) && section->readonly)
|| memory_region_is_romd(section->mr)) { te->addr_write = address | TLB_MMIO; } else if (memory_region_is_ram(section->mr) && !cpu_physical_memory_is_dirty(
section->mr->ram_addr
+ memory_region_section_addr(section, VAR_2))) { te->addr_write = address | TLB_NOTDIRTY; } else { te->addr_write = address; } } else { te->addr_write = -1; } }