static int kvm_mips_get_fpu_registers(CPUState *cs)

{

    MIPSCPU *cpu = MIPS_CPU(cs);

    CPUMIPSState *env = &cpu->env;

    int err, ret = 0;

    unsigned int i;



    /* Only get FPU state if we're emulating a CPU with an FPU */

    if (env->CP0_Config1 & (1 << CP0C1_FP)) {

        /* FPU Control Registers */

        err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR,

                                    &env->active_fpu.fcr0);

        if (err < 0) {

            DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err);

            ret = err;

        }

        err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR,

                                    &env->active_fpu.fcr31);

        if (err < 0) {

            DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err);

            ret = err;

        } else {

            restore_fp_status(env);

        }



        /* Floating point registers */

        for (i = 0; i < 32; ++i) {

            if (env->CP0_Status & (1 << CP0St_FR)) {

                err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i),

                                              &env->active_fpu.fpr[i].d);

            } else {

                err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i),

                                      &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]);

            }

            if (err < 0) {

                DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err);

                ret = err;

            }

        }

    }



    return ret;

}

static int kvm_mips_get_fpu_registers(CPUState *cs)

{

    MIPSCPU *cpu = MIPS_CPU(cs);

    CPUMIPSState *env = &cpu->env;

    int err, ret = 0;

    unsigned int i;



    

    if (env->CP0_Config1 & (1 << CP0C1_FP)) {

        

        err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_IR,

                                    &env->active_fpu.fcr0);

        if (err < 0) {

            DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, err);

            ret = err;

        }

        err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FCR_CSR,

                                    &env->active_fpu.fcr31);

        if (err < 0) {

            DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, err);

            ret = err;

        } else {

            restore_fp_status(env);

        }



        

        for (i = 0; i < 32; ++i) {

            if (env->CP0_Status & (1 << CP0St_FR)) {

                err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i),

                                              &env->active_fpu.fpr[i].d);

            } else {

                err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i),

                                      &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]);

            }

            if (err < 0) {

                DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err);

                ret = err;

            }

        }

    }



    return ret;

}

static int FUNC_0(CPUState *VAR_0)

{

    MIPSCPU *cpu = MIPS_CPU(VAR_0);

    CPUMIPSState *env = &cpu->env;

    int VAR_1, VAR_2 = 0;

    unsigned int VAR_3;



    

    if (env->CP0_Config1 & (1 << CP0C1_FP)) {

        

        VAR_1 = kvm_mips_get_one_ureg(VAR_0, KVM_REG_MIPS_FCR_IR,

                                    &env->active_fpu.fcr0);

        if (VAR_1 < 0) {

            DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, VAR_1);

            VAR_2 = VAR_1;

        }

        VAR_1 = kvm_mips_get_one_ureg(VAR_0, KVM_REG_MIPS_FCR_CSR,

                                    &env->active_fpu.fcr31);

        if (VAR_1 < 0) {

            DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, VAR_1);

            VAR_2 = VAR_1;

        } else {

            restore_fp_status(env);

        }



        

        for (VAR_3 = 0; VAR_3 < 32; ++VAR_3) {

            if (env->CP0_Status & (1 << CP0St_FR)) {

                VAR_1 = kvm_mips_get_one_ureg64(VAR_0, KVM_REG_MIPS_FPR_64(VAR_3),

                                              &env->active_fpu.fpr[VAR_3].d);

            } else {

                VAR_1 = kvm_mips_get_one_ureg(VAR_0, KVM_REG_MIPS_FPR_32(VAR_3),

                                      &env->active_fpu.fpr[VAR_3].w[FP_ENDIAN_IDX]);

            }

            if (VAR_1 < 0) {

                DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, VAR_3, VAR_1);

                VAR_2 = VAR_1;

            }

        }

    }



    return VAR_2;

}

static int FUNC_0(CPUState *VAR_0)
{ MIPSCPU *cpu = MIPS_CPU(VAR_0); CPUMIPSState *env = &cpu->env; int VAR_1, VAR_2 = 0; unsigned int VAR_3; if (env->CP0_Config1 & (1 << CP0C1_FP)) { VAR_1 = kvm_mips_get_one_ureg(VAR_0, KVM_REG_MIPS_FCR_IR,
&env->active_fpu.fcr0); if (VAR_1 < 0) { DPRINTF("%s: Failed to get FCR_IR (%d)\n", __func__, VAR_1); VAR_2 = VAR_1; } VAR_1 = kvm_mips_get_one_ureg(VAR_0, KVM_REG_MIPS_FCR_CSR,
&env->active_fpu.fcr31); if (VAR_1 < 0) { DPRINTF("%s: Failed to get FCR_CSR (%d)\n", __func__, VAR_1); VAR_2 = VAR_1; } else { restore_fp_status(env); } for (VAR_3 = 0; VAR_3 < 32; ++VAR_3) { if (env->CP0_Status & (1 << CP0St_FR)) { VAR_1 = kvm_mips_get_one_ureg64(VAR_0, KVM_REG_MIPS_FPR_64(VAR_3),
&env->active_fpu.fpr[VAR_3].d); } else { VAR_1 = kvm_mips_get_one_ureg(VAR_0, KVM_REG_MIPS_FPR_32(VAR_3),
&env->active_fpu.fpr[VAR_3].w[FP_ENDIAN_IDX]); } if (VAR_1 < 0) { DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, VAR_3, VAR_1); VAR_2 = VAR_1; } } } return VAR_2; }