void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,

                             hwaddr paddr, MemTxAttrs attrs, int prot,

                             int mmu_idx, target_ulong size)

{

    CPUArchState *env = cpu->env_ptr;

    MemoryRegionSection *section;

    unsigned int index;

    target_ulong address;

    target_ulong code_address;

    uintptr_t addend;

    CPUTLBEntry *te;

    hwaddr iotlb, xlat, sz;

    unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;

    int asidx = cpu_asidx_from_attrs(cpu, attrs);



    assert_cpu_is_self(cpu);

    assert(size >= TARGET_PAGE_SIZE);

    if (size != TARGET_PAGE_SIZE) {

        tlb_add_large_page(env, vaddr, size);

    }



    sz = size;

    section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz);

    assert(sz >= TARGET_PAGE_SIZE);



    tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx

              " prot=%x idx=%d\n",

              vaddr, paddr, prot, mmu_idx);



    address = vaddr;

    if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {

        /* IO memory case */

        address |= TLB_MMIO;

        addend = 0;

    } else {

        /* TLB_MMIO for rom/romd handled below */

        addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;

    }



    code_address = address;

    iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,

                                            prot, &address);



    index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    te = &env->tlb_table[mmu_idx][index];



    /* do not discard the translation in te, evict it into a victim tlb */

    env->tlb_v_table[mmu_idx][vidx] = *te;

    env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];



    /* refill the tlb */

    env->iotlb[mmu_idx][index].addr = iotlb - vaddr;

    env->iotlb[mmu_idx][index].attrs = attrs;

    te->addend = addend - vaddr;

    if (prot & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (prot & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (prot & PAGE_WRITE) {

        if ((memory_region_is_ram(section->mr) && section->readonly)

            || memory_region_is_romd(section->mr)) {

            /* Write access calls the I/O callback.  */

            te->addr_write = address | TLB_MMIO;

        } else if (memory_region_is_ram(section->mr)

                   && cpu_physical_memory_is_clean(

                        memory_region_get_ram_addr(section->mr) + xlat)) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,

                             hwaddr paddr, MemTxAttrs attrs, int prot,

                             int mmu_idx, target_ulong size)

{

    CPUArchState *env = cpu->env_ptr;

    MemoryRegionSection *section;

    unsigned int index;

    target_ulong address;

    target_ulong code_address;

    uintptr_t addend;

    CPUTLBEntry *te;

    hwaddr iotlb, xlat, sz;

    unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;

    int asidx = cpu_asidx_from_attrs(cpu, attrs);



    assert_cpu_is_self(cpu);

    assert(size >= TARGET_PAGE_SIZE);

    if (size != TARGET_PAGE_SIZE) {

        tlb_add_large_page(env, vaddr, size);

    }



    sz = size;

    section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz);

    assert(sz >= TARGET_PAGE_SIZE);



    tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx

              " prot=%x idx=%d\n",

              vaddr, paddr, prot, mmu_idx);



    address = vaddr;

    if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {

        

        address |= TLB_MMIO;

        addend = 0;

    } else {

        

        addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;

    }



    code_address = address;

    iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,

                                            prot, &address);



    index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    te = &env->tlb_table[mmu_idx][index];



    

    env->tlb_v_table[mmu_idx][vidx] = *te;

    env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];



    

    env->iotlb[mmu_idx][index].addr = iotlb - vaddr;

    env->iotlb[mmu_idx][index].attrs = attrs;

    te->addend = addend - vaddr;

    if (prot & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (prot & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (prot & PAGE_WRITE) {

        if ((memory_region_is_ram(section->mr) && section->readonly)

            || memory_region_is_romd(section->mr)) {

            

            te->addr_write = address | TLB_MMIO;

        } else if (memory_region_is_ram(section->mr)

                   && cpu_physical_memory_is_clean(

                        memory_region_get_ram_addr(section->mr) + xlat)) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

    assert_cpu_is_self(cpu);     CPUTLBEntry *te;     env->tlb_v_table[mmu_idx][vidx] = *te;     te->addend = addend - vaddr;         te->addr_read = address;         te->addr_read = -1;         te->addr_code = code_address;         te->addr_code = -1;             te->addr_write = address | TLB_MMIO;             te->addr_write = address | TLB_NOTDIRTY;             te->addr_write = address;     } else {         te->addr_write = -1;
void FUNC_0(CPUState *VAR_0, target_ulong VAR_1,

                             hwaddr VAR_2, MemTxAttrs VAR_3, int VAR_4,

                             int VAR_5, target_ulong VAR_6)

{

    CPUArchState *env = VAR_0->env_ptr;

    MemoryRegionSection *section;

    unsigned int VAR_7;

    target_ulong address;

    target_ulong code_address;

    uintptr_t addend;

    CPUTLBEntry *te;

    hwaddr iotlb, xlat, sz;

    unsigned VAR_8 = env->vtlb_index++ % CPU_VTLB_SIZE;

    int VAR_9 = cpu_asidx_from_attrs(VAR_0, VAR_3);



    assert_cpu_is_self(VAR_0);

    assert(VAR_6 >= TARGET_PAGE_SIZE);

    if (VAR_6 != TARGET_PAGE_SIZE) {

        tlb_add_large_page(env, VAR_1, VAR_6);

    }



    sz = VAR_6;

    section = address_space_translate_for_iotlb(VAR_0, VAR_9, VAR_2, &xlat, &sz);

    assert(sz >= TARGET_PAGE_SIZE);



    tlb_debug("VAR_1=" TARGET_FMT_lx " VAR_2=0x" TARGET_FMT_plx

              " VAR_4=%x idx=%d\n",

              VAR_1, VAR_2, VAR_4, VAR_5);



    address = VAR_1;

    if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {

        

        address |= TLB_MMIO;

        addend = 0;

    } else {

        

        addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;

    }



    code_address = address;

    iotlb = memory_region_section_get_iotlb(VAR_0, section, VAR_1, VAR_2, xlat,

                                            VAR_4, &address);



    VAR_7 = (VAR_1 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    te = &env->tlb_table[VAR_5][VAR_7];



    

    env->tlb_v_table[VAR_5][VAR_8] = *te;

    env->iotlb_v[VAR_5][VAR_8] = env->iotlb[VAR_5][VAR_7];



    

    env->iotlb[VAR_5][VAR_7].addr = iotlb - VAR_1;

    env->iotlb[VAR_5][VAR_7].VAR_3 = VAR_3;

    te->addend = addend - VAR_1;

    if (VAR_4 & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (VAR_4 & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (VAR_4 & PAGE_WRITE) {

        if ((memory_region_is_ram(section->mr) && section->readonly)

            || memory_region_is_romd(section->mr)) {

            

            te->addr_write = address | TLB_MMIO;

        } else if (memory_region_is_ram(section->mr)

                   && cpu_physical_memory_is_clean(

                        memory_region_get_ram_addr(section->mr) + xlat)) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

void FUNC_0(CPUState *VAR_0, target_ulong VAR_1,
hwaddr VAR_2, MemTxAttrs VAR_3, int VAR_4,
int VAR_5, target_ulong VAR_6)
{ CPUArchState *env = VAR_0->env_ptr; MemoryRegionSection *section; unsigned int VAR_7; target_ulong address; target_ulong code_address; uintptr_t addend; CPUTLBEntry *te; hwaddr iotlb, xlat, sz; unsigned VAR_8 = env->vtlb_index++ % CPU_VTLB_SIZE; int VAR_9 = cpu_asidx_from_attrs(VAR_0, VAR_3); assert_cpu_is_self(VAR_0); assert(VAR_6 >= TARGET_PAGE_SIZE); if (VAR_6 != TARGET_PAGE_SIZE) { tlb_add_large_page(env, VAR_1, VAR_6); } sz = VAR_6; section = address_space_translate_for_iotlb(VAR_0, VAR_9, VAR_2, &xlat, &sz); assert(sz >= TARGET_PAGE_SIZE); tlb_debug("VAR_1=" TARGET_FMT_lx " VAR_2=0x" TARGET_FMT_plx
" VAR_4=%x idx=%d\n",
VAR_1, VAR_2, VAR_4, VAR_5); address = VAR_1; if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { address |= TLB_MMIO; addend = 0; } else { addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat; } code_address = address; iotlb = memory_region_section_get_iotlb(VAR_0, section, VAR_1, VAR_2, xlat,
VAR_4, &address); VAR_7 = (VAR_1 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); te = &env->tlb_table[VAR_5][VAR_7]; env->tlb_v_table[VAR_5][VAR_8] = *te; env->iotlb_v[VAR_5][VAR_8] = env->iotlb[VAR_5][VAR_7]; env->iotlb[VAR_5][VAR_7].addr = iotlb - VAR_1; env->iotlb[VAR_5][VAR_7].VAR_3 = VAR_3; te->addend = addend - VAR_1; if (VAR_4 & PAGE_READ) { te->addr_read = address; } else { te->addr_read = -1; } if (VAR_4 & PAGE_EXEC) { te->addr_code = code_address; } else { te->addr_code = -1; } if (VAR_4 & PAGE_WRITE) { if ((memory_region_is_ram(section->mr) && section->readonly)
|| memory_region_is_romd(section->mr)) { te->addr_write = address | TLB_MMIO; } else if (memory_region_is_ram(section->mr) && cpu_physical_memory_is_clean(
memory_region_get_ram_addr(section->mr) + xlat)) { te->addr_write = address | TLB_NOTDIRTY; } else { te->addr_write = address; } } else { te->addr_write = -1; } }