static void gen_mtfsfi(DisasContext *ctx)

{

    int bf, sh;

    TCGv_i64 t0;

    TCGv_i32 t1;



    if (unlikely(!ctx->fpu_enabled)) {

        gen_exception(ctx, POWERPC_EXCP_FPU);

        return;

    }

    bf = crbD(ctx->opcode) >> 2;

    sh = 7 - bf;

    /* NIP cannot be restored if the memory exception comes from an helper */

    gen_update_nip(ctx, ctx->nip - 4);

    gen_reset_fpstatus();

    t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));

    t1 = tcg_const_i32(1 << sh);

    gen_helper_store_fpscr(cpu_env, t0, t1);

    tcg_temp_free_i64(t0);

    tcg_temp_free_i32(t1);

    if (unlikely(Rc(ctx->opcode) != 0)) {

        tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);

        tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);

    }

    /* We can raise a differed exception */

    gen_helper_float_check_status(cpu_env);

}

static void gen_mtfsfi(DisasContext *ctx)

{

    int bf, sh;

    TCGv_i64 t0;

    TCGv_i32 t1;



    if (unlikely(!ctx->fpu_enabled)) {

        gen_exception(ctx, POWERPC_EXCP_FPU);

        return;

    }

    bf = crbD(ctx->opcode) >> 2;

    sh = 7 - bf;

    

    gen_update_nip(ctx, ctx->nip - 4);

    gen_reset_fpstatus();

    t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));

    t1 = tcg_const_i32(1 << sh);

    gen_helper_store_fpscr(cpu_env, t0, t1);

    tcg_temp_free_i64(t0);

    tcg_temp_free_i32(t1);

    if (unlikely(Rc(ctx->opcode) != 0)) {

        tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);

        tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);

    }

    

    gen_helper_float_check_status(cpu_env);

}

static void FUNC_0(DisasContext *VAR_0)

{

    int VAR_1, VAR_2;

    TCGv_i64 t0;

    TCGv_i32 t1;



    if (unlikely(!VAR_0->fpu_enabled)) {

        gen_exception(VAR_0, POWERPC_EXCP_FPU);

        return;

    }

    VAR_1 = crbD(VAR_0->opcode) >> 2;

    VAR_2 = 7 - VAR_1;

    

    gen_update_nip(VAR_0, VAR_0->nip - 4);

    gen_reset_fpstatus();

    t0 = tcg_const_i64(FPIMM(VAR_0->opcode) << (4 * VAR_2));

    t1 = tcg_const_i32(1 << VAR_2);

    gen_helper_store_fpscr(cpu_env, t0, t1);

    tcg_temp_free_i64(t0);

    tcg_temp_free_i32(t1);

    if (unlikely(Rc(VAR_0->opcode) != 0)) {

        tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);

        tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);

    }

    

    gen_helper_float_check_status(cpu_env);

}

static void FUNC_0(DisasContext *VAR_0)
{ int VAR_1, VAR_2; TCGv_i64 t0; TCGv_i32 t1; if (unlikely(!VAR_0->fpu_enabled)) { gen_exception(VAR_0, POWERPC_EXCP_FPU); return; } VAR_1 = crbD(VAR_0->opcode) >> 2; VAR_2 = 7 - VAR_1; gen_update_nip(VAR_0, VAR_0->nip - 4); gen_reset_fpstatus(); t0 = tcg_const_i64(FPIMM(VAR_0->opcode) << (4 * VAR_2)); t1 = tcg_const_i32(1 << VAR_2); gen_helper_store_fpscr(cpu_env, t0, t1); tcg_temp_free_i64(t0); tcg_temp_free_i32(t1); if (unlikely(Rc(VAR_0->opcode) != 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } gen_helper_float_check_status(cpu_env); }