static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,

                         int base, int16_t offset)

{

    const char *opn = "st_cond";

    TCGv t0, t1;



    t0 = tcg_temp_local_new();



    gen_base_offset_addr(ctx, t0, base, offset);

    /* Don't do NOP if destination is zero: we must perform the actual

       memory access. */



    t1 = tcg_temp_local_new();

    gen_load_gpr(t1, rt);

    switch (opc) {

#if defined(TARGET_MIPS64)

    case OPC_SCD:

        save_cpu_state(ctx, 0);

        op_st_scd(t1, t0, rt, ctx);

        opn = "scd";

        break;

#endif

    case OPC_SC:

        save_cpu_state(ctx, 1);

        op_st_sc(t1, t0, rt, ctx);

        opn = "sc";

        break;

    }

    (void)opn; /* avoid a compiler warning */

    MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);

    tcg_temp_free(t1);

    tcg_temp_free(t0);

}

static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,

                         int base, int16_t offset)

{

    const char *opn = "st_cond";

    TCGv t0, t1;



    t0 = tcg_temp_local_new();



    gen_base_offset_addr(ctx, t0, base, offset);

    





    t1 = tcg_temp_local_new();

    gen_load_gpr(t1, rt);

    switch (opc) {

#if defined(TARGET_MIPS64)

    case OPC_SCD:

        save_cpu_state(ctx, 0);

        op_st_scd(t1, t0, rt, ctx);

        opn = "scd";

        break;

#endif

    case OPC_SC:

        save_cpu_state(ctx, 1);

        op_st_sc(t1, t0, rt, ctx);

        opn = "sc";

        break;

    }

    (void)opn; 

    MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);

    tcg_temp_free(t1);

    tcg_temp_free(t0);

}

        save_cpu_state(ctx, 0);         save_cpu_state(ctx, 1);         save_cpu_state(ctx, 1);         save_cpu_state(ctx, 0);         save_cpu_state(ctx, 1);         save_cpu_state(ctx, 1);
static void FUNC_0 (DisasContext *VAR_0, uint32_t VAR_1, int VAR_2,

                         int VAR_3, int16_t VAR_4)

{

    const char *VAR_5 = "st_cond";

    TCGv t0, t1;



    t0 = tcg_temp_local_new();



    gen_base_offset_addr(VAR_0, t0, VAR_3, VAR_4);

    





    t1 = tcg_temp_local_new();

    gen_load_gpr(t1, VAR_2);

    switch (VAR_1) {

#if defined(TARGET_MIPS64)

    case OPC_SCD:

        save_cpu_state(VAR_0, 0);

        op_st_scd(t1, t0, VAR_2, VAR_0);

        VAR_5 = "scd";

        break;

#endif

    case OPC_SC:

        save_cpu_state(VAR_0, 1);

        op_st_sc(t1, t0, VAR_2, VAR_0);

        VAR_5 = "sc";

        break;

    }

    (void)VAR_5; 

    MIPS_DEBUG("%s %s, %d(%s)", VAR_5, regnames[VAR_2], VAR_4, regnames[VAR_3]);

    tcg_temp_free(t1);

    tcg_temp_free(t0);

}

static void FUNC_0 (DisasContext *VAR_0, uint32_t VAR_1, int VAR_2,
int VAR_3, int16_t VAR_4)
{ const char *VAR_5 = "st_cond"; TCGv t0, t1; t0 = tcg_temp_local_new(); gen_base_offset_addr(VAR_0, t0, VAR_3, VAR_4); t1 = tcg_temp_local_new(); gen_load_gpr(t1, VAR_2); switch (VAR_1) { #if defined(TARGET_MIPS64)
case OPC_SCD:
save_cpu_state(VAR_0, 0); op_st_scd(t1, t0, VAR_2, VAR_0); VAR_5 = "scd"; break; #endif
case OPC_SC:
save_cpu_state(VAR_0, 1); op_st_sc(t1, t0, VAR_2, VAR_0); VAR_5 = "sc"; break; } (void)VAR_5; MIPS_DEBUG("%s %s, %d(%s)", VAR_5, regnames[VAR_2], VAR_4, regnames[VAR_3]); tcg_temp_free(t1); tcg_temp_free(t0); }