void tlb_set_page(CPUState *env, target_ulong vaddr,

                  target_phys_addr_t paddr, int prot,

                  int mmu_idx, target_ulong size)

{

    PhysPageDesc *p;

    unsigned long pd;

    unsigned int index;

    target_ulong address;

    target_ulong code_address;

    unsigned long addend;

    CPUTLBEntry *te;

    CPUWatchpoint *wp;

    target_phys_addr_t iotlb;



    assert(size >= TARGET_PAGE_SIZE);

    if (size != TARGET_PAGE_SIZE) {

        tlb_add_large_page(env, vaddr, size);

    }

    p = phys_page_find(paddr >> TARGET_PAGE_BITS);

    if (!p) {

        pd = IO_MEM_UNASSIGNED;

    } else {

        pd = p->phys_offset;

    }

#if defined(DEBUG_TLB)

    printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",

           vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);

#endif



    address = vaddr;

    if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {

        /* IO memory case (romd handled later) */

        address |= TLB_MMIO;

    }

    addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);

    if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {

        /* Normal RAM.  */

        iotlb = pd & TARGET_PAGE_MASK;

        if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)

            iotlb |= IO_MEM_NOTDIRTY;

        else

            iotlb |= IO_MEM_ROM;

    } else {

        /* IO handlers are currently passed a physical address.

           It would be nice to pass an offset from the base address

           of that region.  This would avoid having to special case RAM,

           and avoid full address decoding in every device.

           We can't use the high bits of pd for this because

           IO_MEM_ROMD uses these as a ram address.  */

        iotlb = (pd & ~TARGET_PAGE_MASK);

        if (p) {

            iotlb += p->region_offset;

        } else {

            iotlb += paddr;

        }

    }



    code_address = address;

    /* Make accesses to pages with watchpoints go via the

       watchpoint trap routines.  */

    QTAILQ_FOREACH(wp, &env->watchpoints, entry) {

        if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {

            iotlb = io_mem_watch + paddr;

            /* TODO: The memory case can be optimized by not trapping

               reads of pages with a write breakpoint.  */

            address |= TLB_MMIO;

        }

    }



    index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    env->iotlb[mmu_idx][index] = iotlb - vaddr;

    te = &env->tlb_table[mmu_idx][index];

    te->addend = addend - vaddr;

    if (prot & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (prot & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (prot & PAGE_WRITE) {

        if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||

            (pd & IO_MEM_ROMD)) {

            /* Write access calls the I/O callback.  */

            te->addr_write = address | TLB_MMIO;

        } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&

                   !cpu_physical_memory_is_dirty(pd)) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

void tlb_set_page(CPUState *env, target_ulong vaddr,

                  target_phys_addr_t paddr, int prot,

                  int mmu_idx, target_ulong size)

{

    PhysPageDesc *p;

    unsigned long pd;

    unsigned int index;

    target_ulong address;

    target_ulong code_address;

    unsigned long addend;

    CPUTLBEntry *te;

    CPUWatchpoint *wp;

    target_phys_addr_t iotlb;



    assert(size >= TARGET_PAGE_SIZE);

    if (size != TARGET_PAGE_SIZE) {

        tlb_add_large_page(env, vaddr, size);

    }

    p = phys_page_find(paddr >> TARGET_PAGE_BITS);

    if (!p) {

        pd = IO_MEM_UNASSIGNED;

    } else {

        pd = p->phys_offset;

    }

#if defined(DEBUG_TLB)

    printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",

           vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);

#endif



    address = vaddr;

    if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {

        

        address |= TLB_MMIO;

    }

    addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);

    if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {

        

        iotlb = pd & TARGET_PAGE_MASK;

        if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)

            iotlb |= IO_MEM_NOTDIRTY;

        else

            iotlb |= IO_MEM_ROM;

    } else {

        











        iotlb = (pd & ~TARGET_PAGE_MASK);

        if (p) {

            iotlb += p->region_offset;

        } else {

            iotlb += paddr;

        }

    }



    code_address = address;

    



    QTAILQ_FOREACH(wp, &env->watchpoints, entry) {

        if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {

            iotlb = io_mem_watch + paddr;

            



            address |= TLB_MMIO;

        }

    }



    index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    env->iotlb[mmu_idx][index] = iotlb - vaddr;

    te = &env->tlb_table[mmu_idx][index];

    te->addend = addend - vaddr;

    if (prot & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (prot & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (prot & PAGE_WRITE) {

        if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||

            (pd & IO_MEM_ROMD)) {

            

            te->addr_write = address | TLB_MMIO;

        } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&

                   !cpu_physical_memory_is_dirty(pd)) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

void FUNC_0(CPUState *VAR_0, target_ulong VAR_1,

                  target_phys_addr_t VAR_2, int VAR_3,

                  int VAR_4, target_ulong VAR_5)

{

    PhysPageDesc *p;

    unsigned long VAR_6;

    unsigned int VAR_7;

    target_ulong address;

    target_ulong code_address;

    unsigned long VAR_8;

    CPUTLBEntry *te;

    CPUWatchpoint *wp;

    target_phys_addr_t iotlb;



    assert(VAR_5 >= TARGET_PAGE_SIZE);

    if (VAR_5 != TARGET_PAGE_SIZE) {

        tlb_add_large_page(VAR_0, VAR_1, VAR_5);

    }

    p = phys_page_find(VAR_2 >> TARGET_PAGE_BITS);

    if (!p) {

        VAR_6 = IO_MEM_UNASSIGNED;

    } else {

        VAR_6 = p->phys_offset;

    }

#if defined(DEBUG_TLB)

    printf("FUNC_0: VAR_1=" TARGET_FMT_lx " VAR_2=0x%08x VAR_3=%x idx=%d smmu=%d VAR_6=0x%08lx\n",

           VAR_1, (int)VAR_2, VAR_3, VAR_4, is_softmmu, VAR_6);

#endif



    address = VAR_1;

    if ((VAR_6 & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(VAR_6 & IO_MEM_ROMD)) {

        

        address |= TLB_MMIO;

    }

    VAR_8 = (unsigned long)qemu_get_ram_ptr(VAR_6 & TARGET_PAGE_MASK);

    if ((VAR_6 & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {

        

        iotlb = VAR_6 & TARGET_PAGE_MASK;

        if ((VAR_6 & ~TARGET_PAGE_MASK) == IO_MEM_RAM)

            iotlb |= IO_MEM_NOTDIRTY;

        else

            iotlb |= IO_MEM_ROM;

    } else {

        











        iotlb = (VAR_6 & ~TARGET_PAGE_MASK);

        if (p) {

            iotlb += p->region_offset;

        } else {

            iotlb += VAR_2;

        }

    }



    code_address = address;

    



    QTAILQ_FOREACH(wp, &VAR_0->watchpoints, entry) {

        if (VAR_1 == (wp->VAR_1 & TARGET_PAGE_MASK)) {

            iotlb = io_mem_watch + VAR_2;

            



            address |= TLB_MMIO;

        }

    }



    VAR_7 = (VAR_1 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

    VAR_0->iotlb[VAR_4][VAR_7] = iotlb - VAR_1;

    te = &VAR_0->tlb_table[VAR_4][VAR_7];

    te->VAR_8 = VAR_8 - VAR_1;

    if (VAR_3 & PAGE_READ) {

        te->addr_read = address;

    } else {

        te->addr_read = -1;

    }



    if (VAR_3 & PAGE_EXEC) {

        te->addr_code = code_address;

    } else {

        te->addr_code = -1;

    }

    if (VAR_3 & PAGE_WRITE) {

        if ((VAR_6 & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||

            (VAR_6 & IO_MEM_ROMD)) {

            

            te->addr_write = address | TLB_MMIO;

        } else if ((VAR_6 & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&

                   !cpu_physical_memory_is_dirty(VAR_6)) {

            te->addr_write = address | TLB_NOTDIRTY;

        } else {

            te->addr_write = address;

        }

    } else {

        te->addr_write = -1;

    }

}

void FUNC_0(CPUState *VAR_0, target_ulong VAR_1,
target_phys_addr_t VAR_2, int VAR_3,
int VAR_4, target_ulong VAR_5)
{ PhysPageDesc *p; unsigned long VAR_6; unsigned int VAR_7; target_ulong address; target_ulong code_address; unsigned long VAR_8; CPUTLBEntry *te; CPUWatchpoint *wp; target_phys_addr_t iotlb; assert(VAR_5 >= TARGET_PAGE_SIZE); if (VAR_5 != TARGET_PAGE_SIZE) { tlb_add_large_page(VAR_0, VAR_1, VAR_5); } p = phys_page_find(VAR_2 >> TARGET_PAGE_BITS); if (!p) { VAR_6 = IO_MEM_UNASSIGNED; } else { VAR_6 = p->phys_offset; } #if defined(DEBUG_TLB)
printf("FUNC_0: VAR_1=" TARGET_FMT_lx " VAR_2=0x%08x VAR_3=%x idx=%d smmu=%d VAR_6=0x%08lx\n",
VAR_1, (int)VAR_2, VAR_3, VAR_4, is_softmmu, VAR_6); #endif
address = VAR_1; if ((VAR_6 & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(VAR_6 & IO_MEM_ROMD)) { address |= TLB_MMIO; } VAR_8 = (unsigned long)qemu_get_ram_ptr(VAR_6 & TARGET_PAGE_MASK); if ((VAR_6 & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { iotlb = VAR_6 & TARGET_PAGE_MASK; if ((VAR_6 & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
iotlb |= IO_MEM_NOTDIRTY; else
iotlb |= IO_MEM_ROM; } else { iotlb = (VAR_6 & ~TARGET_PAGE_MASK); if (p) { iotlb += p->region_offset; } else { iotlb += VAR_2; } } code_address = address; QTAILQ_FOREACH(wp, &VAR_0->watchpoints, entry) { if (VAR_1 == (wp->VAR_1 & TARGET_PAGE_MASK)) { iotlb = io_mem_watch + VAR_2; address |= TLB_MMIO; } } VAR_7 = (VAR_1 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); VAR_0->iotlb[VAR_4][VAR_7] = iotlb - VAR_1; te = &VAR_0->tlb_table[VAR_4][VAR_7]; te->VAR_8 = VAR_8 - VAR_1; if (VAR_3 & PAGE_READ) { te->addr_read = address; } else { te->addr_read = -1; } if (VAR_3 & PAGE_EXEC) { te->addr_code = code_address; } else { te->addr_code = -1; } if (VAR_3 & PAGE_WRITE) { if ((VAR_6 & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
(VAR_6 & IO_MEM_ROMD)) { te->addr_write = address | TLB_MMIO; } else if ((VAR_6 & ~TARGET_PAGE_MASK) == IO_MEM_RAM && !cpu_physical_memory_is_dirty(VAR_6)) { te->addr_write = address | TLB_NOTDIRTY; } else { te->addr_write = address; } } else { te->addr_write = -1; } }