static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn,

                              TCGReg r1, TCGReg r2, TCGReg rn,

                              tcg_target_long ofs, bool pre, bool w)

{

    insn |= 1u << 31; /* ext */

    insn |= pre << 24;

    insn |= w << 23;



    assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0);

    insn |= (ofs & (0x7f << 3)) << (15 - 3);



    tcg_out32(s, insn | r2 << 10 | rn << 5 | r1);

}

static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn,

                              TCGReg r1, TCGReg r2, TCGReg rn,

                              tcg_target_long ofs, bool pre, bool w)

{

    insn |= 1u << 31; 

    insn |= pre << 24;

    insn |= w << 23;



    assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0);

    insn |= (ofs & (0x7f << 3)) << (15 - 3);



    tcg_out32(s, insn | r2 << 10 | rn << 5 | r1);

}

static void FUNC_0(TCGContext *VAR_0, AArch64Insn VAR_1,

                              TCGReg VAR_2, TCGReg VAR_3, TCGReg VAR_4,

                              tcg_target_long VAR_5, bool VAR_6, bool VAR_7)

{

    VAR_1 |= 1u << 31; 

    VAR_1 |= VAR_6 << 24;

    VAR_1 |= VAR_7 << 23;



    assert(VAR_5 >= -0x200 && VAR_5 < 0x200 && (VAR_5 & 7) == 0);

    VAR_1 |= (VAR_5 & (0x7f << 3)) << (15 - 3);



    tcg_out32(VAR_0, VAR_1 | VAR_3 << 10 | VAR_4 << 5 | VAR_2);

}

static void FUNC_0(TCGContext *VAR_0, AArch64Insn VAR_1,
TCGReg VAR_2, TCGReg VAR_3, TCGReg VAR_4,
tcg_target_long VAR_5, bool VAR_6, bool VAR_7)
{ VAR_1 |= 1u << 31; VAR_1 |= VAR_6 << 24; VAR_1 |= VAR_7 << 23; assert(VAR_5 >= -0x200 && VAR_5 < 0x200 && (VAR_5 & 7) == 0); VAR_1 |= (VAR_5 & (0x7f << 3)) << (15 - 3); tcg_out32(VAR_0, VAR_1 | VAR_3 << 10 | VAR_4 << 5 | VAR_2); }