static void spapr_msi_write(void *opaque, hwaddr addr,

                            uint64_t data, unsigned size)

{

    sPAPRPHBState *phb = opaque;

    int ndev = addr >> 16;

    int vec = ((addr & 0xFFFF) >> 2) | data;

    uint32_t irq = phb->msi_table[ndev].irq + vec;



    trace_spapr_pci_msi_write(addr, data, irq);



    qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));

}

static void spapr_msi_write(void *opaque, hwaddr addr,

                            uint64_t data, unsigned size)

{

    sPAPRPHBState *phb = opaque;

    int ndev = addr >> 16;

    int vec = ((addr & 0xFFFF) >> 2) | data;

    uint32_t irq = phb->msi_table[ndev].irq + vec;



    trace_spapr_pci_msi_write(addr, data, irq);



    qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,

                            uint64_t VAR_2, unsigned VAR_3)

{

    sPAPRPHBState *phb = VAR_0;

    int VAR_4 = VAR_1 >> 16;

    int VAR_5 = ((VAR_1 & 0xFFFF) >> 2) | VAR_2;

    uint32_t irq = phb->msi_table[VAR_4].irq + VAR_5;



    trace_spapr_pci_msi_write(VAR_1, VAR_2, irq);



    qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ sPAPRPHBState *phb = VAR_0; int VAR_4 = VAR_1 >> 16; int VAR_5 = ((VAR_1 & 0xFFFF) >> 2) | VAR_2; uint32_t irq = phb->msi_table[VAR_4].irq + VAR_5; trace_spapr_pci_msi_write(VAR_1, VAR_2, irq); qemu_irq_pulse(xics_get_qirq(spapr->icp, irq)); }