int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,

                              int mmu_idx)

{

    MIPSCPU *cpu = MIPS_CPU(cs);

    CPUMIPSState *env = &cpu->env;

#if !defined(CONFIG_USER_ONLY)

    hwaddr physical;

    int prot;

    int access_type;

#endif

    int ret = 0;



#if 0

    log_cpu_state(cs, 0);

#endif

    qemu_log_mask(CPU_LOG_MMU,

              "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",

              __func__, env->active_tc.PC, address, rw, mmu_idx);



    /* data access */

#if !defined(CONFIG_USER_ONLY)

    /* XXX: put correct access by using cpu_restore_state()

       correctly */

    access_type = ACCESS_INT;

    ret = get_physical_address(env, &physical, &prot,

                               address, rw, access_type);

    qemu_log_mask(CPU_LOG_MMU,

             "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx

             " prot %d\n",

             __func__, address, ret, physical, prot);

    if (ret == TLBRET_MATCH) {

        tlb_set_page(cs, address & TARGET_PAGE_MASK,

                     physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,

                     mmu_idx, TARGET_PAGE_SIZE);

        ret = 0;

    } else if (ret < 0)

#endif

    {

        raise_mmu_exception(env, address, rw, ret);

        ret = 1;

    }



    return ret;

}

int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,

                              int mmu_idx)

{

    MIPSCPU *cpu = MIPS_CPU(cs);

    CPUMIPSState *env = &cpu->env;

#if !defined(CONFIG_USER_ONLY)

    hwaddr physical;

    int prot;

    int access_type;

#endif

    int ret = 0;



#if 0

    log_cpu_state(cs, 0);

#endif

    qemu_log_mask(CPU_LOG_MMU,

              "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",

              __func__, env->active_tc.PC, address, rw, mmu_idx);



    

#if !defined(CONFIG_USER_ONLY)

    



    access_type = ACCESS_INT;

    ret = get_physical_address(env, &physical, &prot,

                               address, rw, access_type);

    qemu_log_mask(CPU_LOG_MMU,

             "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx

             " prot %d\n",

             __func__, address, ret, physical, prot);

    if (ret == TLBRET_MATCH) {

        tlb_set_page(cs, address & TARGET_PAGE_MASK,

                     physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,

                     mmu_idx, TARGET_PAGE_SIZE);

        ret = 0;

    } else if (ret < 0)

#endif

    {

        raise_mmu_exception(env, address, rw, ret);

        ret = 1;

    }



    return ret;

}

    qemu_log_mask(CPU_LOG_MMU,              "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx              " prot %d\n",              __func__, address, ret, physical, prot);
int FUNC_0(CPUState *VAR_0, vaddr VAR_1, int VAR_2,

                              int VAR_3)

{

    MIPSCPU *cpu = MIPS_CPU(VAR_0);

    CPUMIPSState *env = &cpu->env;

#if !defined(CONFIG_USER_ONLY)

    hwaddr physical;

    int VAR_4;

    int VAR_5;

#endif

    int VAR_6 = 0;



#if 0

    log_cpu_state(VAR_0, 0);

#endif

    qemu_log_mask(CPU_LOG_MMU,

              "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " VAR_2 %d VAR_3 %d\n",

              __func__, env->active_tc.PC, VAR_1, VAR_2, VAR_3);



    

#if !defined(CONFIG_USER_ONLY)

    



    VAR_5 = ACCESS_INT;

    VAR_6 = get_physical_address(env, &physical, &VAR_4,

                               VAR_1, VAR_2, VAR_5);

    qemu_log_mask(CPU_LOG_MMU,

             "%s VAR_1=%" VADDR_PRIx " VAR_6 %d physical " TARGET_FMT_plx

             " VAR_4 %d\n",

             __func__, VAR_1, VAR_6, physical, VAR_4);

    if (VAR_6 == TLBRET_MATCH) {

        tlb_set_page(VAR_0, VAR_1 & TARGET_PAGE_MASK,

                     physical & TARGET_PAGE_MASK, VAR_4 | PAGE_EXEC,

                     VAR_3, TARGET_PAGE_SIZE);

        VAR_6 = 0;

    } else if (VAR_6 < 0)

#endif

    {

        raise_mmu_exception(env, VAR_1, VAR_2, VAR_6);

        VAR_6 = 1;

    }



    return VAR_6;

}

int FUNC_0(CPUState *VAR_0, vaddr VAR_1, int VAR_2,
int VAR_3)
{ MIPSCPU *cpu = MIPS_CPU(VAR_0); CPUMIPSState *env = &cpu->env; #if !defined(CONFIG_USER_ONLY)
hwaddr physical; int VAR_4; int VAR_5; #endif
int VAR_6 = 0; #if 0
log_cpu_state(VAR_0, 0); #endif
qemu_log_mask(CPU_LOG_MMU,
"%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " VAR_2 %d VAR_3 %d\n",
__func__, env->active_tc.PC, VAR_1, VAR_2, VAR_3); #if !defined(CONFIG_USER_ONLY)
VAR_5 = ACCESS_INT; VAR_6 = get_physical_address(env, &physical, &VAR_4,
VAR_1, VAR_2, VAR_5); qemu_log_mask(CPU_LOG_MMU,
"%s VAR_1=%" VADDR_PRIx " VAR_6 %d physical " TARGET_FMT_plx
" VAR_4 %d\n",
__func__, VAR_1, VAR_6, physical, VAR_4); if (VAR_6 == TLBRET_MATCH) { tlb_set_page(VAR_0, VAR_1 & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, VAR_4 | PAGE_EXEC,
VAR_3, TARGET_PAGE_SIZE); VAR_6 = 0; } else if (VAR_6 < 0) #endif
{ raise_mmu_exception(env, VAR_1, VAR_2, VAR_6); VAR_6 = 1; } return VAR_6; }