static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,

                                                  TranslationBlock *tb,

                                                  int search_pc)

{

    CPUState *cs = CPU(cpu);

    struct DisasContext ctx, *dc = &ctx;

    uint16_t *gen_opc_end;

    uint32_t pc_start;

    int j, k;

    uint32_t next_page_start;

    int num_insns;

    int max_insns;



    pc_start = tb->pc;

    dc->tb = tb;



    gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;

    dc->is_jmp = DISAS_NEXT;

    dc->ppc = pc_start;

    dc->pc = pc_start;

    dc->flags = cpu->env.cpucfgr;

    dc->mem_idx = cpu_mmu_index(&cpu->env);

    dc->synced_flags = dc->tb_flags = tb->flags;

    dc->delayed_branch = !!(dc->tb_flags & D_FLAG);

    dc->singlestep_enabled = cs->singlestep_enabled;

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {

        qemu_log("-----------------------------------------\n");

        log_cpu_state(CPU(cpu), 0);

    }



    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    k = -1;

    num_insns = 0;

    max_insns = tb->cflags & CF_COUNT_MASK;



    if (max_insns == 0) {

        max_insns = CF_COUNT_MASK;

    }



    gen_tb_start();



    do {

        check_breakpoint(cpu, dc);

        if (search_pc) {

            j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

            if (k < j) {

                k++;

                while (k < j) {

                    tcg_ctx.gen_opc_instr_start[k++] = 0;

                }

            }

            tcg_ctx.gen_opc_pc[k] = dc->pc;

            tcg_ctx.gen_opc_instr_start[k] = 1;

            tcg_ctx.gen_opc_icount[k] = num_insns;

        }



        if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {

            tcg_gen_debug_insn_start(dc->pc);

        }



        if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {

            gen_io_start();

        }

        dc->ppc = dc->pc - 4;

        dc->npc = dc->pc + 4;

        tcg_gen_movi_tl(cpu_ppc, dc->ppc);

        tcg_gen_movi_tl(cpu_npc, dc->npc);

        disas_openrisc_insn(dc, cpu);

        dc->pc = dc->npc;

        num_insns++;

        /* delay slot */

        if (dc->delayed_branch) {

            dc->delayed_branch--;

            if (!dc->delayed_branch) {

                dc->tb_flags &= ~D_FLAG;

                gen_sync_flags(dc);

                tcg_gen_mov_tl(cpu_pc, jmp_pc);

                tcg_gen_mov_tl(cpu_npc, jmp_pc);

                tcg_gen_movi_tl(jmp_pc, 0);

                tcg_gen_exit_tb(0);

                dc->is_jmp = DISAS_JUMP;

                break;

            }

        }

    } while (!dc->is_jmp

             && tcg_ctx.gen_opc_ptr < gen_opc_end

             && !cs->singlestep_enabled

             && !singlestep

             && (dc->pc < next_page_start)

             && num_insns < max_insns);



    if (tb->cflags & CF_LAST_IO) {

        gen_io_end();

    }

    if (dc->is_jmp == DISAS_NEXT) {

        dc->is_jmp = DISAS_UPDATE;

        tcg_gen_movi_tl(cpu_pc, dc->pc);

    }

    if (unlikely(cs->singlestep_enabled)) {

        if (dc->is_jmp == DISAS_NEXT) {

            tcg_gen_movi_tl(cpu_pc, dc->pc);

        }

        gen_exception(dc, EXCP_DEBUG);

    } else {

        switch (dc->is_jmp) {

        case DISAS_NEXT:

            gen_goto_tb(dc, 0, dc->pc);

            break;

        default:

        case DISAS_JUMP:

            break;

        case DISAS_UPDATE:

            /* indicate that the hash table must be used

               to find the next TB */

            tcg_gen_exit_tb(0);

            break;

        case DISAS_TB_JUMP:

            /* nothing more to generate */

            break;

        }

    }



    gen_tb_end(tb, num_insns);

    *tcg_ctx.gen_opc_ptr = INDEX_op_end;

    if (search_pc) {

        j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

        k++;

        while (k <= j) {

            tcg_ctx.gen_opc_instr_start[k++] = 0;

        }

    } else {

        tb->size = dc->pc - pc_start;

        tb->icount = num_insns;

    }



#ifdef DEBUG_DISAS

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {

        qemu_log("\n");

        log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0);

        qemu_log("\nisize=%d osize=%td\n",

            dc->pc - pc_start, tcg_ctx.gen_opc_ptr -

            tcg_ctx.gen_opc_buf);

    }

#endif

}

static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,

                                                  TranslationBlock *tb,

                                                  int search_pc)

{

    CPUState *cs = CPU(cpu);

    struct DisasContext ctx, *dc = &ctx;

    uint16_t *gen_opc_end;

    uint32_t pc_start;

    int j, k;

    uint32_t next_page_start;

    int num_insns;

    int max_insns;



    pc_start = tb->pc;

    dc->tb = tb;



    gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;

    dc->is_jmp = DISAS_NEXT;

    dc->ppc = pc_start;

    dc->pc = pc_start;

    dc->flags = cpu->env.cpucfgr;

    dc->mem_idx = cpu_mmu_index(&cpu->env);

    dc->synced_flags = dc->tb_flags = tb->flags;

    dc->delayed_branch = !!(dc->tb_flags & D_FLAG);

    dc->singlestep_enabled = cs->singlestep_enabled;

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {

        qemu_log("-----------------------------------------\n");

        log_cpu_state(CPU(cpu), 0);

    }



    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    k = -1;

    num_insns = 0;

    max_insns = tb->cflags & CF_COUNT_MASK;



    if (max_insns == 0) {

        max_insns = CF_COUNT_MASK;

    }



    gen_tb_start();



    do {

        check_breakpoint(cpu, dc);

        if (search_pc) {

            j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

            if (k < j) {

                k++;

                while (k < j) {

                    tcg_ctx.gen_opc_instr_start[k++] = 0;

                }

            }

            tcg_ctx.gen_opc_pc[k] = dc->pc;

            tcg_ctx.gen_opc_instr_start[k] = 1;

            tcg_ctx.gen_opc_icount[k] = num_insns;

        }



        if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {

            tcg_gen_debug_insn_start(dc->pc);

        }



        if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {

            gen_io_start();

        }

        dc->ppc = dc->pc - 4;

        dc->npc = dc->pc + 4;

        tcg_gen_movi_tl(cpu_ppc, dc->ppc);

        tcg_gen_movi_tl(cpu_npc, dc->npc);

        disas_openrisc_insn(dc, cpu);

        dc->pc = dc->npc;

        num_insns++;

        

        if (dc->delayed_branch) {

            dc->delayed_branch--;

            if (!dc->delayed_branch) {

                dc->tb_flags &= ~D_FLAG;

                gen_sync_flags(dc);

                tcg_gen_mov_tl(cpu_pc, jmp_pc);

                tcg_gen_mov_tl(cpu_npc, jmp_pc);

                tcg_gen_movi_tl(jmp_pc, 0);

                tcg_gen_exit_tb(0);

                dc->is_jmp = DISAS_JUMP;

                break;

            }

        }

    } while (!dc->is_jmp

             && tcg_ctx.gen_opc_ptr < gen_opc_end

             && !cs->singlestep_enabled

             && !singlestep

             && (dc->pc < next_page_start)

             && num_insns < max_insns);



    if (tb->cflags & CF_LAST_IO) {

        gen_io_end();

    }

    if (dc->is_jmp == DISAS_NEXT) {

        dc->is_jmp = DISAS_UPDATE;

        tcg_gen_movi_tl(cpu_pc, dc->pc);

    }

    if (unlikely(cs->singlestep_enabled)) {

        if (dc->is_jmp == DISAS_NEXT) {

            tcg_gen_movi_tl(cpu_pc, dc->pc);

        }

        gen_exception(dc, EXCP_DEBUG);

    } else {

        switch (dc->is_jmp) {

        case DISAS_NEXT:

            gen_goto_tb(dc, 0, dc->pc);

            break;

        default:

        case DISAS_JUMP:

            break;

        case DISAS_UPDATE:

            



            tcg_gen_exit_tb(0);

            break;

        case DISAS_TB_JUMP:

            

            break;

        }

    }



    gen_tb_end(tb, num_insns);

    *tcg_ctx.gen_opc_ptr = INDEX_op_end;

    if (search_pc) {

        j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

        k++;

        while (k <= j) {

            tcg_ctx.gen_opc_instr_start[k++] = 0;

        }

    } else {

        tb->size = dc->pc - pc_start;

        tb->icount = num_insns;

    }



#ifdef DEBUG_DISAS

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {

        qemu_log("\n");

        log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0);

        qemu_log("\nisize=%d osize=%td\n",

            dc->pc - pc_start, tcg_ctx.gen_opc_ptr -

            tcg_ctx.gen_opc_buf);

    }

#endif

}

static inline void FUNC_0(OpenRISCCPU *VAR_0,

                                                  TranslationBlock *VAR_1,

                                                  int VAR_2)

{

    CPUState *cs = CPU(VAR_0);

    struct DisasContext VAR_3, *VAR_4 = &VAR_3;

    uint16_t *gen_opc_end;

    uint32_t pc_start;

    int VAR_5, VAR_6;

    uint32_t next_page_start;

    int VAR_7;

    int VAR_8;



    pc_start = VAR_1->pc;

    VAR_4->VAR_1 = VAR_1;



    gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;

    VAR_4->is_jmp = DISAS_NEXT;

    VAR_4->ppc = pc_start;

    VAR_4->pc = pc_start;

    VAR_4->flags = VAR_0->env.cpucfgr;

    VAR_4->mem_idx = cpu_mmu_index(&VAR_0->env);

    VAR_4->synced_flags = VAR_4->tb_flags = VAR_1->flags;

    VAR_4->delayed_branch = !!(VAR_4->tb_flags & D_FLAG);

    VAR_4->singlestep_enabled = cs->singlestep_enabled;

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {

        qemu_log("-----------------------------------------\n");

        log_cpu_state(CPU(VAR_0), 0);

    }



    next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    VAR_6 = -1;

    VAR_7 = 0;

    VAR_8 = VAR_1->cflags & CF_COUNT_MASK;



    if (VAR_8 == 0) {

        VAR_8 = CF_COUNT_MASK;

    }



    gen_tb_start();



    do {

        check_breakpoint(VAR_0, VAR_4);

        if (VAR_2) {

            VAR_5 = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

            if (VAR_6 < VAR_5) {

                VAR_6++;

                while (VAR_6 < VAR_5) {

                    tcg_ctx.gen_opc_instr_start[VAR_6++] = 0;

                }

            }

            tcg_ctx.gen_opc_pc[VAR_6] = VAR_4->pc;

            tcg_ctx.gen_opc_instr_start[VAR_6] = 1;

            tcg_ctx.gen_opc_icount[VAR_6] = VAR_7;

        }



        if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {

            tcg_gen_debug_insn_start(VAR_4->pc);

        }



        if (VAR_7 + 1 == VAR_8 && (VAR_1->cflags & CF_LAST_IO)) {

            gen_io_start();

        }

        VAR_4->ppc = VAR_4->pc - 4;

        VAR_4->npc = VAR_4->pc + 4;

        tcg_gen_movi_tl(cpu_ppc, VAR_4->ppc);

        tcg_gen_movi_tl(cpu_npc, VAR_4->npc);

        disas_openrisc_insn(VAR_4, VAR_0);

        VAR_4->pc = VAR_4->npc;

        VAR_7++;

        

        if (VAR_4->delayed_branch) {

            VAR_4->delayed_branch--;

            if (!VAR_4->delayed_branch) {

                VAR_4->tb_flags &= ~D_FLAG;

                gen_sync_flags(VAR_4);

                tcg_gen_mov_tl(cpu_pc, jmp_pc);

                tcg_gen_mov_tl(cpu_npc, jmp_pc);

                tcg_gen_movi_tl(jmp_pc, 0);

                tcg_gen_exit_tb(0);

                VAR_4->is_jmp = DISAS_JUMP;

                break;

            }

        }

    } while (!VAR_4->is_jmp

             && tcg_ctx.gen_opc_ptr < gen_opc_end

             && !cs->singlestep_enabled

             && !singlestep

             && (VAR_4->pc < next_page_start)

             && VAR_7 < VAR_8);



    if (VAR_1->cflags & CF_LAST_IO) {

        gen_io_end();

    }

    if (VAR_4->is_jmp == DISAS_NEXT) {

        VAR_4->is_jmp = DISAS_UPDATE;

        tcg_gen_movi_tl(cpu_pc, VAR_4->pc);

    }

    if (unlikely(cs->singlestep_enabled)) {

        if (VAR_4->is_jmp == DISAS_NEXT) {

            tcg_gen_movi_tl(cpu_pc, VAR_4->pc);

        }

        gen_exception(VAR_4, EXCP_DEBUG);

    } else {

        switch (VAR_4->is_jmp) {

        case DISAS_NEXT:

            gen_goto_tb(VAR_4, 0, VAR_4->pc);

            break;

        default:

        case DISAS_JUMP:

            break;

        case DISAS_UPDATE:

            



            tcg_gen_exit_tb(0);

            break;

        case DISAS_TB_JUMP:

            

            break;

        }

    }



    gen_tb_end(VAR_1, VAR_7);

    *tcg_ctx.gen_opc_ptr = INDEX_op_end;

    if (VAR_2) {

        VAR_5 = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;

        VAR_6++;

        while (VAR_6 <= VAR_5) {

            tcg_ctx.gen_opc_instr_start[VAR_6++] = 0;

        }

    } else {

        VAR_1->size = VAR_4->pc - pc_start;

        VAR_1->icount = VAR_7;

    }



#ifdef DEBUG_DISAS

    if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {

        qemu_log("\n");

        log_target_disas(&VAR_0->env, pc_start, VAR_4->pc - pc_start, 0);

        qemu_log("\nisize=%d osize=%td\n",

            VAR_4->pc - pc_start, tcg_ctx.gen_opc_ptr -

            tcg_ctx.gen_opc_buf);

    }

#endif

}

static inline void FUNC_0(OpenRISCCPU *VAR_0,
TranslationBlock *VAR_1,
int VAR_2)
{ CPUState *cs = CPU(VAR_0); struct DisasContext VAR_3, *VAR_4 = &VAR_3; uint16_t *gen_opc_end; uint32_t pc_start; int VAR_5, VAR_6; uint32_t next_page_start; int VAR_7; int VAR_8; pc_start = VAR_1->pc; VAR_4->VAR_1 = VAR_1; gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; VAR_4->is_jmp = DISAS_NEXT; VAR_4->ppc = pc_start; VAR_4->pc = pc_start; VAR_4->flags = VAR_0->env.cpucfgr; VAR_4->mem_idx = cpu_mmu_index(&VAR_0->env); VAR_4->synced_flags = VAR_4->tb_flags = VAR_1->flags; VAR_4->delayed_branch = !!(VAR_4->tb_flags & D_FLAG); VAR_4->singlestep_enabled = cs->singlestep_enabled; if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("-----------------------------------------\n"); log_cpu_state(CPU(VAR_0), 0); } next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; VAR_6 = -1; VAR_7 = 0; VAR_8 = VAR_1->cflags & CF_COUNT_MASK; if (VAR_8 == 0) { VAR_8 = CF_COUNT_MASK; } gen_tb_start(); do { check_breakpoint(VAR_0, VAR_4); if (VAR_2) { VAR_5 = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; if (VAR_6 < VAR_5) { VAR_6++; while (VAR_6 < VAR_5) { tcg_ctx.gen_opc_instr_start[VAR_6++] = 0; } } tcg_ctx.gen_opc_pc[VAR_6] = VAR_4->pc; tcg_ctx.gen_opc_instr_start[VAR_6] = 1; tcg_ctx.gen_opc_icount[VAR_6] = VAR_7; } if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { tcg_gen_debug_insn_start(VAR_4->pc); } if (VAR_7 + 1 == VAR_8 && (VAR_1->cflags & CF_LAST_IO)) { gen_io_start(); } VAR_4->ppc = VAR_4->pc - 4; VAR_4->npc = VAR_4->pc + 4; tcg_gen_movi_tl(cpu_ppc, VAR_4->ppc); tcg_gen_movi_tl(cpu_npc, VAR_4->npc); disas_openrisc_insn(VAR_4, VAR_0); VAR_4->pc = VAR_4->npc; VAR_7++; if (VAR_4->delayed_branch) { VAR_4->delayed_branch--; if (!VAR_4->delayed_branch) { VAR_4->tb_flags &= ~D_FLAG; gen_sync_flags(VAR_4); tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_mov_tl(cpu_npc, jmp_pc); tcg_gen_movi_tl(jmp_pc, 0); tcg_gen_exit_tb(0); VAR_4->is_jmp = DISAS_JUMP; break; } } } while (!VAR_4->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end
&& !cs->singlestep_enabled
&& !singlestep
&& (VAR_4->pc < next_page_start)
&& VAR_7 < VAR_8); if (VAR_1->cflags & CF_LAST_IO) { gen_io_end(); } if (VAR_4->is_jmp == DISAS_NEXT) { VAR_4->is_jmp = DISAS_UPDATE; tcg_gen_movi_tl(cpu_pc, VAR_4->pc); } if (unlikely(cs->singlestep_enabled)) { if (VAR_4->is_jmp == DISAS_NEXT) { tcg_gen_movi_tl(cpu_pc, VAR_4->pc); } gen_exception(VAR_4, EXCP_DEBUG); } else { switch (VAR_4->is_jmp) { case DISAS_NEXT:
gen_goto_tb(VAR_4, 0, VAR_4->pc); break; default:
case DISAS_JUMP:
break; case DISAS_UPDATE:
tcg_gen_exit_tb(0); break; case DISAS_TB_JUMP:
break; } } gen_tb_end(VAR_1, VAR_7); *tcg_ctx.gen_opc_ptr = INDEX_op_end; if (VAR_2) { VAR_5 = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; VAR_6++; while (VAR_6 <= VAR_5) { tcg_ctx.gen_opc_instr_start[VAR_6++] = 0; } } else { VAR_1->size = VAR_4->pc - pc_start; VAR_1->icount = VAR_7; } #ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("\n"); log_target_disas(&VAR_0->env, pc_start, VAR_4->pc - pc_start, 0); qemu_log("\nisize=%d osize=%td\n",
VAR_4->pc - pc_start, tcg_ctx.gen_opc_ptr -
tcg_ctx.gen_opc_buf); } #endif
}