static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)

{

    EHCIState *s = ptr;

    uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);

    uint32_t old = *mmio;

    int i;



    trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);



    /* Only aligned reads are allowed on OHCI */

    if (addr & 3) {

        fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"

                TARGET_FMT_plx "\n", addr);

        return;

    }



    if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {

        handle_port_status_write(s, (addr-PORTSC)/4, val);

        trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);

        return;

    }



    if (addr < OPREGBASE) {

        fprintf(stderr, "usb-ehci: write attempt to read-only register"

                TARGET_FMT_plx "\n", addr);

        return;

    }





    /* Do any register specific pre-write processing here.  */

    switch(addr) {

    case USBCMD:

        if (val & USBCMD_HCRESET) {

            ehci_reset(s);

            val = s->usbcmd;

            break;

        }



        if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=

            ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {

            if (!ehci_enabled(s)) {

                qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));

                SET_LAST_RUN_CLOCK(s);

            }

            ehci_update_halt(s);

        }



        /* not supporting dynamic frame list size at the moment */

        if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {

            fprintf(stderr, "attempt to set frame list size -- value %d\n",

                    val & USBCMD_FLS);

            val &= ~USBCMD_FLS;

        }

        break;



    case USBSTS:

        val &= USBSTS_RO_MASK;              // bits 6 through 31 are RO

        ehci_clear_usbsts(s, val);          // bits 0 through 5 are R/WC

        val = s->usbsts;

        ehci_set_interrupt(s, 0);

        break;



    case USBINTR:

        val &= USBINTR_MASK;

        break;



    case FRINDEX:

        val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */

        break;



    case CONFIGFLAG:

        val &= 0x1;

        if (val) {

            for(i = 0; i < NB_PORTS; i++)

                handle_port_owner_write(s, i, 0);

        }

        break;



    case PERIODICLISTBASE:

        if (ehci_periodic_enabled(s)) {

            fprintf(stderr,

              "ehci: PERIODIC list base register set while periodic schedule\n"

              "      is enabled and HC is enabled\n");

        }

        break;



    case ASYNCLISTADDR:

        if (ehci_async_enabled(s)) {

            fprintf(stderr,

              "ehci: ASYNC list address register set while async schedule\n"

              "      is enabled and HC is enabled\n");

        }

        break;

    }



    *mmio = val;

    trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);

}

static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)

{

    EHCIState *s = ptr;

    uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);

    uint32_t old = *mmio;

    int i;



    trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);



    

    if (addr & 3) {

        fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"

                TARGET_FMT_plx "\n", addr);

        return;

    }



    if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {

        handle_port_status_write(s, (addr-PORTSC)/4, val);

        trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);

        return;

    }



    if (addr < OPREGBASE) {

        fprintf(stderr, "usb-ehci: write attempt to read-only register"

                TARGET_FMT_plx "\n", addr);

        return;

    }





    

    switch(addr) {

    case USBCMD:

        if (val & USBCMD_HCRESET) {

            ehci_reset(s);

            val = s->usbcmd;

            break;

        }



        if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=

            ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {

            if (!ehci_enabled(s)) {

                qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));

                SET_LAST_RUN_CLOCK(s);

            }

            ehci_update_halt(s);

        }



        

        if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {

            fprintf(stderr, "attempt to set frame list size -- value %d\n",

                    val & USBCMD_FLS);

            val &= ~USBCMD_FLS;

        }

        break;



    case USBSTS:

        val &= USBSTS_RO_MASK;              

        ehci_clear_usbsts(s, val);          

        val = s->usbsts;

        ehci_set_interrupt(s, 0);

        break;



    case USBINTR:

        val &= USBINTR_MASK;

        break;



    case FRINDEX:

        val &= 0x00003ff8; 

        break;



    case CONFIGFLAG:

        val &= 0x1;

        if (val) {

            for(i = 0; i < NB_PORTS; i++)

                handle_port_owner_write(s, i, 0);

        }

        break;



    case PERIODICLISTBASE:

        if (ehci_periodic_enabled(s)) {

            fprintf(stderr,

              "ehci: PERIODIC list base register set while periodic schedule\n"

              "      is enabled and HC is enabled\n");

        }

        break;



    case ASYNCLISTADDR:

        if (ehci_async_enabled(s)) {

            fprintf(stderr,

              "ehci: ASYNC list address register set while async schedule\n"

              "      is enabled and HC is enabled\n");

        }

        break;

    }



    *mmio = val;

    trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint32_t VAR_2)

{

    EHCIState *s = VAR_0;

    uint32_t *mmio = (uint32_t *)(&s->mmio[VAR_1]);

    uint32_t old = *mmio;

    int VAR_3;



    trace_usb_ehci_mmio_writel(VAR_1, addr2str(VAR_1), VAR_2);



    

    if (VAR_1 & 3) {

        fprintf(stderr, "usb-ehci: Mis-aligned write to VAR_1 0x"

                TARGET_FMT_plx "\n", VAR_1);

        return;

    }



    if (VAR_1 >= PORTSC && VAR_1 < PORTSC + 4 * NB_PORTS) {

        handle_port_status_write(s, (VAR_1-PORTSC)/4, VAR_2);

        trace_usb_ehci_mmio_change(VAR_1, addr2str(VAR_1), *mmio, old);

        return;

    }



    if (VAR_1 < OPREGBASE) {

        fprintf(stderr, "usb-ehci: write attempt to read-only register"

                TARGET_FMT_plx "\n", VAR_1);

        return;

    }





    

    switch(VAR_1) {

    case USBCMD:

        if (VAR_2 & USBCMD_HCRESET) {

            ehci_reset(s);

            VAR_2 = s->usbcmd;

            break;

        }



        if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & VAR_2) !=

            ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {

            if (!ehci_enabled(s)) {

                qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));

                SET_LAST_RUN_CLOCK(s);

            }

            ehci_update_halt(s);

        }



        

        if ((VAR_2 & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {

            fprintf(stderr, "attempt to set frame list size -- value %d\n",

                    VAR_2 & USBCMD_FLS);

            VAR_2 &= ~USBCMD_FLS;

        }

        break;



    case USBSTS:

        VAR_2 &= USBSTS_RO_MASK;              

        ehci_clear_usbsts(s, VAR_2);          

        VAR_2 = s->usbsts;

        ehci_set_interrupt(s, 0);

        break;



    case USBINTR:

        VAR_2 &= USBINTR_MASK;

        break;



    case FRINDEX:

        VAR_2 &= 0x00003ff8; 

        break;



    case CONFIGFLAG:

        VAR_2 &= 0x1;

        if (VAR_2) {

            for(VAR_3 = 0; VAR_3 < NB_PORTS; VAR_3++)

                handle_port_owner_write(s, VAR_3, 0);

        }

        break;



    case PERIODICLISTBASE:

        if (ehci_periodic_enabled(s)) {

            fprintf(stderr,

              "ehci: PERIODIC list base register set while periodic schedule\n"

              "      is enabled and HC is enabled\n");

        }

        break;



    case ASYNCLISTADDR:

        if (ehci_async_enabled(s)) {

            fprintf(stderr,

              "ehci: ASYNC list address register set while async schedule\n"

              "      is enabled and HC is enabled\n");

        }

        break;

    }



    *mmio = VAR_2;

    trace_usb_ehci_mmio_change(VAR_1, addr2str(VAR_1), *mmio, old);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1, uint32_t VAR_2)
{ EHCIState *s = VAR_0; uint32_t *mmio = (uint32_t *)(&s->mmio[VAR_1]); uint32_t old = *mmio; int VAR_3; trace_usb_ehci_mmio_writel(VAR_1, addr2str(VAR_1), VAR_2); if (VAR_1 & 3) { fprintf(stderr, "usb-ehci: Mis-aligned write to VAR_1 0x"
TARGET_FMT_plx "\n", VAR_1); return; } if (VAR_1 >= PORTSC && VAR_1 < PORTSC + 4 * NB_PORTS) { handle_port_status_write(s, (VAR_1-PORTSC)/4, VAR_2); trace_usb_ehci_mmio_change(VAR_1, addr2str(VAR_1), *mmio, old); return; } if (VAR_1 < OPREGBASE) { fprintf(stderr, "usb-ehci: write attempt to read-only register"
TARGET_FMT_plx "\n", VAR_1); return; } switch(VAR_1) { case USBCMD:
if (VAR_2 & USBCMD_HCRESET) { ehci_reset(s); VAR_2 = s->usbcmd; break; } if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & VAR_2) !=
((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { if (!ehci_enabled(s)) { qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); SET_LAST_RUN_CLOCK(s); } ehci_update_halt(s); } if ((VAR_2 & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { fprintf(stderr, "attempt to set frame list size -- value %d\n",
VAR_2 & USBCMD_FLS); VAR_2 &= ~USBCMD_FLS; } break; case USBSTS:
VAR_2 &= USBSTS_RO_MASK; ehci_clear_usbsts(s, VAR_2); VAR_2 = s->usbsts; ehci_set_interrupt(s, 0); break; case USBINTR:
VAR_2 &= USBINTR_MASK; break; case FRINDEX:
VAR_2 &= 0x00003ff8; break; case CONFIGFLAG:
VAR_2 &= 0x1; if (VAR_2) { for(VAR_3 = 0; VAR_3 < NB_PORTS; VAR_3++) handle_port_owner_write(s, VAR_3, 0); } break; case PERIODICLISTBASE:
if (ehci_periodic_enabled(s)) { fprintf(stderr,
"ehci: PERIODIC list base register set while periodic schedule\n"
"      is enabled and HC is enabled\n"); } break; case ASYNCLISTADDR:
if (ehci_async_enabled(s)) { fprintf(stderr,
"ehci: ASYNC list address register set while async schedule\n"
"      is enabled and HC is enabled\n"); } break; } *mmio = VAR_2; trace_usb_ehci_mmio_change(VAR_1, addr2str(VAR_1), *mmio, old); }