int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                                int mmu_idx, int is_softmmu)

{

    target_ulong phys;

    int prot;



    /* XXX: implement mmu */



    phys = address;

    prot = PAGE_READ | PAGE_WRITE;



    return tlb_set_page(env, address & TARGET_PAGE_MASK,

                        phys & TARGET_PAGE_MASK, prot,

                        mmu_idx, is_softmmu);

}

int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                                int mmu_idx, int is_softmmu)

{

    target_ulong phys;

    int prot;



    



    phys = address;

    prot = PAGE_READ | PAGE_WRITE;



    return tlb_set_page(env, address & TARGET_PAGE_MASK,

                        phys & TARGET_PAGE_MASK, prot,

                        mmu_idx, is_softmmu);

}

int FUNC_0 (CPUState *VAR_0, target_ulong VAR_1, int VAR_2,

                                int VAR_3, int VAR_4)

{

    target_ulong phys;

    int VAR_5;



    



    phys = VAR_1;

    VAR_5 = PAGE_READ | PAGE_WRITE;



    return tlb_set_page(VAR_0, VAR_1 & TARGET_PAGE_MASK,

                        phys & TARGET_PAGE_MASK, VAR_5,

                        VAR_3, VAR_4);

}

int FUNC_0 (CPUState *VAR_0, target_ulong VAR_1, int VAR_2,
int VAR_3, int VAR_4)
{ target_ulong phys; int VAR_5; phys = VAR_1; VAR_5 = PAGE_READ | PAGE_WRITE; return tlb_set_page(VAR_0, VAR_1 & TARGET_PAGE_MASK,
phys & TARGET_PAGE_MASK, VAR_5,
VAR_3, VAR_4); }